As known in the art, a dynamic random access memory (DRAM) device is made up of memory cells. Each cell of a DRAM device comprises a transistor and a capacitor electrically coupled to a terminal such as the drain (or source) of the transistor. A digit line is electrically coupled to another terminal such as the source (or drain) of the transistor. The memory cells are addressed via a word line and the digit line, one of which addresses a “column” of memory cells while the other addresses a “row” of the memory cells.
One type of the typical DRAM device utilizes buried word line (BWL) architecture comprising parallel word lines embedded in a cell array. The buried word lines are fabricated in word line trenches that intersect with the active areas (AAs). The capacitor is stacked on a major surface of the silicon substrate and the digit line is constructed over the major surface of the silicon substrate and over the capacitor.
As the size of DRAM cell shrinks, the surface area of the AA becomes smaller and smaller. The decreasing surface area of the AAs results in insufficient cell contact area (or landing area) for the capacitors and decreased process window when forming a cell contact layer (or landing pad). Additionally, there is a continuing goal to further decrease the cell area. Therefore, it has become a major issue in this technical field to cope with the insufficient cell contact area and narrow process window.